1. Field of the Invention
The present invention relates to a central processing unit forming a major part of a data processing system and, more particularly, to an instruction decoder and a decoder control for the data processing system.
1. Description of related art.
Heretofore, a so-called central processing unit comprises, for example, an instruction prefetch unit 101, an instruction decode unit 102, an address translation unit 103, an instruction execution unit 104, and a bus interface 105, respectively, as shown in FIG. 1. The instruction prefetch unit 101 has an instruction queue memory for storing an instruction code prefetched from the bus interface 105 and reads the prefetched instruction code from the instruction queue memory in response to a request of the instruction decode unit 102. The instruction decode unit 102 decodes the instruction code read out of the instruction prefetch unit 101 to issue a control information to the instruction execution unit 104. The instruction decode unit 102 computes the effective address of a memory operand and requests the address translation unit 103 an address translation. The address translation unit 103 conducts a translation from a virtual address into a real address and transfers the translation result to the bus interface 105. The instruction execution unit 104 executes an operation on the basis of the control information sent from the instruction decode unit 102. The bus interface 105 accesses an external memory on the basis of the real address sent from the address translation unit 103 and prefetches an instruction for the instruction prefetch unit 101.
FIG. 2 shows in more detail the instruction decode unit 102 and the address translation unit 103 shown in FIG. 1. Reference numeral 801 denotes the instruction queue memory built in the instruction prefetch unit 101 for storing an instruction code. Reference Numeral 802 denotes an instruction-code/operand-field decoder of the instruction decode unit 102. Further, an address computation section 803 is provided for computing the addresses of an effective address operand and a memory operand on the basis of the decoded result of an operand field. The effective address computed by the address computation section 803 is translated by an address translator 804 from a virtual address into a real address in the case of the memory operand, and the real address is sent to the bus interface 105. The address translator 804 corresponds to the address translation unit 103 of FIG. 1. In addition, an instruction buffer 805 is provided for transferring the decoded information obtained by the instruction decoder 802 to the instruction execution unit 104.
In the data processing system thus constructed, an instruction is first sent from the instruction queue memory 801 to the instruction decoder 802. This instruction decoder 802 decodes an information concerning the instruction code such as the kind of an arithmetic algorithm and sets the result in the instruction buffer 805. Then, the instruction decoder 802 decodes the operand part of the instruction. At this time, in case the operand is a memory operand, the instruction decoder 802 instructs the address computation section 803 to perform an effective address computation. The address computation section 803 sends the computed effective address to the address translator 804, in which the virtual address is translated into a real address. This real address is sent to the bus interface 105 so that the memory operand may be fetched. The instruction decoder 802 is informed, from the address translator 804 through the address computation section 803, of whether the address has been translated exceptionally by a page fault or a protection exception or normally. The instruction decoder 802 sets the instruction buffer 805 with an information indicating an instruction executability, if the address translation is normal, and an information indicating an exception processing start, if the translation is exceptional. Then, the instruction execution unit 104 is started.
On the basis of the information read out of the instruction buffer 805, the instruction execution unit 104 executes the instruction. If, however, a translation exception is read out of the instruction buffer 805, the instruction execution unit 104 executes a corresponding processing such as the page fault and requests the instruction decode unit 102 a redecode of the instruction. In the case of no translation exception when the instruction is decoded, the instruction execution unit 104 requests the instruction decode unit 102 to start the decoding of a next instruction at the instant when its instruction execution is completed.
Usually, under the virtual memory management, in the case that the operand has its address translated exceptionally as in the page fault, the instruction cannot be executed before the operand address is settled after its decoding. For example, in case the page fault occurs, the instruction need be re-executed after the exception is processed by the operating system. Despite of this necessity, however, the system of the prior art described above can neither process the address translation exception nor execute the instruction unless the execution of the instruction is conducted after the completion of decoding the instruction. The decoding of a next instruction is started at the completion of the execution of the previous instruction. As a result, the data processing system of the prior art has a defect that it cannot conduct the instruction decoding and execution in parallel under the virtual memory management to improve its performance.